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ics9248-199 integrated circuit systems, inc. 0376e?12/23/02 frequency generator for sis 735/740 with amd k7 processor recommended application: main system clock for sis 735/740 with amd k7 chipset. output features: 1 - cpu @ 2.5v 1 - differential pair open drain cpu clock 1 - ioapic @ 2.5v 1 - sdram @ 3.3v 6- pci @3.3v 2 - agp @ 3.3v 1- 48mhz, @3.3v fixed 1- 24/48mhz, @3.3v selectable by i 2 c (default is 24mhz) 2- ref @3.3v, 14.318mhz pin configuration 48-pin 300mil ssop vddref ref0 *fs1/ref1 gnd gnd x1 x2 gnd vddpci pciclk1 pciclk2 gnd pciclk3 pciclk4 vddagp agpclk0 agpclk1 gnd vdd48 48mhz agpsel/ 24_48mhz gnd 2 2 *fs0/ 2 2 21 fs2/pciclk_f fs3/pciclk0 **fs4/ ** ** ** 2 vddlapic ioapic* gnd vddl cpuclkt0 cpuclkc0 gnd vddl cpuclk gnd nc nc vddsdr sdram gnd pci_stop# cpu_stop# pd# sdram_stop# agp_stop# s data sclk gnd vdd 2 2 1 2 2 ics9248-199 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 note: please see full table on page 4. frequency table features: programmable output frequency. programmable output divider ratios. programmable output rise/fall time. programmable output skew. programmable spread percentage for emi control. watchdog timer technology to reset system if system malfunctions. programmable watch dog safe frequency. support i 2 c index read/write and block read/write operations. uses external 14.318mhz crystal. skew specifications: cpu - cpu: < 175ps pci - pci: < 500ps cpu - sdram: < 250ps agp - agp: <175ps cpu - agp, pci: 1-4ns * these are double strength. ** (1x/2x) have single or double strength to drive 2 loads. 1. internal pull-up, of 120k to v dd . 2. these inputs have a 120k pull down to gnd. bit 2 bit 7 bit 6 bit 5 bit 4 cpu sdram pci agp sel = 0 agp sel = 1 fs4 fs3 fs2 fs1 fs0 0 0 0 0 0 66.66 66.66 33.33 66.66 50.00 0 0 0 0 1 100.00 100.00 33.33 66.66 50.00 0 0 0 1 0 166.66 166.66 33.33 66.66 55.60 0 0 0 1 1 133.33 133.33 33.33 66.66 50.00 0 0 1 0 0 66.66 100.00 33.33 66.66 50.00 0 0 1 0 1 100.00 66.66 33.33 66.66 50.00 0 0 1 1 0 100.00 133.33 33.33 66.66 50.00 0 0 1 1 1 133.33 100.00 33.33 66.66 50.00 0 1 0 0 0 112.00 112.00 33.60 67.20 56.00 0 1 0 0 1 124.00 124.00 31.00 62.00 46.50 0 1 0 1 0 138.00 138.00 34.50 69.00 46.00 0 1 0 1 1 150.00 150.00 30.00 60.00 50.00 0 1 1 0 0 100.00 166.66 31.25 62.50 50.00 0 1 1 0 1 133.33 166.66 33.33 66.66 55.30 0 1 1 1 0 150.00 100.00 30.00 60.00 50.00 0 1 1 1 1 160.00 120.00 30.00 60.00 48.00 1 0 0 0 0 90.00 90.00 30.00 60.00 45.00 1 0 0 0 1 100.90 100.90 33.63 67.27 50.45 1 0 0 1 0 103.00 103.00 34.33 68.67 51.50 1 0 0 1 1 133.90 133.90 33.48 68.67 51.56 1 0 1 0 0 137.33 103.00 34.33 66.95 51.45 1 0 1 0 1 137.33 137.33 34.33 68.67 50.21 1 0 1 1 0 100.90 133.90 33.48 66.95 50.21 1 0 1 1 1 133.90 100.90 33.48 66.95 50.21 1 1 0 0 0 107.00 107.00 35.66 71.33 53.50 1 1 0 0 1 107.00 142.66 35.66 71.33 53.50 1 1 0 1 0 142.66 142.66 35.66 71.33 53.50 1 1 0 1 1 110.00 110.00 36.66 73.33 55.00 1 1 1 0 0 110.00 146.66 36.66 73.33 55.00 1 1 1 0 1 146.66 146.66 36.66 73.33 55.00 1 1 1 1 0 166.70 125.00 31.25 66.68 55.57 1 1 1 1 1 200.00 200.00 33.33 66.66 50.00
2 ics9248-199 0376e?12/23/02 pin configuration pin number pin name type description 1, 11, 17, 21, 25, 36 vdd pwr 3.3v power supply for sdram output buffers, pci output buffers, reference output buffers and 48mhz output. fs0 in frequency select pin. ref0 out 14.318 mhz reference clock. fs1 in frequency select pin. ref1 out 14.318 mhz reference clock. 4, 5, 8, 14, 20, 24, 26, 34, 39, 42, 46 gnd pwr ground pin for outputs. 6 x1 in crystal input,nominally 14.318mhz. 7 x2 out crystal output, nominally 14.318mhz. fs2 in frequency select pin. pciclk_f out pci clock output, not affected by pci_stop#. fs3 in frequency select pin. pciclk0 out pci clock output. fs4 in frequency select pin. pciclk1 out pci clock output. 16, 15, 13 pciclk (4:2) out pci clock outputs. 19, 18 agpclk (1:0) out agp outputs defined as 2x pci. these may not be stopped. 22 48mhz out 48mhz output clock. agpsel in agp freq uency select pin. 24_48mhz out clock output for super i/o/usb default is 24mhz. 27 sclk in clock pin of i 2 c circuitry 5v tolerant. 28 sdata i/o data pin for i 2 c circuitry 5v tolerant. 29 agp_stop# in stops all agp clocks besides the agp_f clocks at logic 0 level, when input low. 30 sdram_stop# in stops all sdram clocks at logic 0 level, when i nput low (when mode active). 31 pd# in asynchronous active low input pin used to power down the device into a low power state. the internal clocks are disabled and the vco and the crystal are stopped. the latency of the power down will not be greater than 3ms. 32 cpu_stop# in stops all cpuclks clocks at logic 0 level, when i nput low. 33 pci_stop# in stops all pciclks besides the pciclk_f clocks at logic 0 level, when input low. 35 sdram out sdram clock output. 37, 38 nc - no connect pins. 40 cpuclk out cpu clock output. 41, 45, 48 vddl pwr supply for cpu and ioapic clo cks at 2.5v nominal. 43 cpuclkc0 out complementary clocks of differential pair cpu outputs. this clock is 180 out of phase with sdram clocks. these open drain outputs need an external 1.5v pull-up. 44 cpuclkt0 out "true" clocks of differential pair cpu outputs. this clock is in phase with sdram clocks. this open drain output needs an external 1.5v pull-up. 47 ioapic out 2.5v clock output. 2 9 10 23 3 12
3 ics9248-199 0376e?12/23/02 general description power groups vddcpu = cpu vddpci = pciclk_f, pciclk vddsdr = sdram vdd48 = 48mhz, 24mhz, fixed pll vdda = core, pll, x1, x2 vddagp=agp, ref the ics9248-199 is a single chip clock solution for desktop designs using the intel brookdale chipset with pc133 or ddr memory. it provides all necessary clock signals for such a system. the ics9248-199 is part of a whole new line of ics clock generators and buffers called tch? (timing control hub). this part incorporates ics's newest clock technology which offers more robust features and functionality. employing the use of a serially programmable i 2 c interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. m/n control can configure output frequency with resolution up to 0.1mhz increment. pll2 pll1 spread spectrum 48mhz 24_48mhz cpuclk sdram pciclk (4:0) agpclk (1:0) ioapic pciclk_f 2 5 2 x1 x2 xtal osc cpu divder sdram divder pci divder stop stop stop s data sclk fs (4:0) pd# pci_stop# cpu_stop# sdram_stop# agp_stop# agp_sel control logic config. reg. / 2 ref (1:0) agp divder stop ioapic divder cpuclkt0 cpuclkc0 block diagram
4 ics9248-199 0376e?12/23/02 serial configuration command bitmap note: pwd = power-up default i 2 c is a trademark of philips corporation note1: default at power-up will be for latched logic inputs to define frequency, as defined by bit 3. byte4: functionality and frequency select register (default = 0) bytes 0-3: are reserved for external clock buffer. t i bn o i t p i r c s e dd w p 2 t i b 4 : 7 t i b 2 t i b7 t i b6 t i b5 t i b4 t i b u p cm a r d si c p p g a 0 = l e s p g a 1 = l e s e g a t n e c e r p d a e r p s 0 0 0 0 0 1 e t o n 4 s f3 s f2 s f1 s f0 s f 000 0 0 6 6 . 6 66 6 . 6 63 3 . 3 36 6 . 6 60 0 . 0 5d a e r p s n w o d % 5 . 0 - o t 0 000 0 1 0 0 . 0 0 10 0 . 0 0 13 3 . 3 36 6 . 6 60 0 . 0 5d a e r p s n w o d % 5 . 0 - o t 0 000 1 0 6 6 . 6 6 16 6 . 6 6 13 3 . 3 36 6 . 6 60 6 . 5 5d a e r p s r e t n e c % 5 2 . 0 - / + 000 1 1 3 3 . 3 3 13 3 . 3 3 13 3 . 3 36 6 . 6 60 0 . 0 5d a e r p s n w o d % 5 . 0 - o t 0 00 10 0 6 6 . 6 60 0 . 0 0 13 3 . 3 36 6 . 6 60 0 . 0 5d a e r p s n w o d % 5 . 0 - o t 0 00 10 1 0 0 . 0 0 16 6 . 6 63 3 . 3 36 6 . 6 60 0 . 0 5d a e r p s n w o d % 5 . 0 - o t 0 00 1 1 0 0 0 . 0 0 13 3 . 3 3 13 3 . 3 36 6 . 6 60 0 . 0 5d a e r p s n w o d % 5 . 0 - o t 0 00 1 1 1 3 3 . 3 3 10 0 . 0 0 13 3 . 3 36 6 . 6 60 0 . 0 5d a e r p s n w o d % 5 . 0 - o t 0 0100 0 0 0 . 2 1 10 0 . 2 1 10 6 . 3 30 2 . 7 60 0 . 6 5d a e r p s r e t n e c % 5 2 . 0 - / + 0100 1 0 0 . 4 2 10 0 . 4 2 10 0 . 1 30 0 . 2 60 5 . 6 4d a e r p s r e t n e c % 5 2 . 0 - / + 010 10 0 0 . 8 3 10 0 . 8 3 10 5 . 4 30 0 . 9 60 0 . 6 4d a e r p s r e t n e c % 5 2 . 0 - / + 010 1 1 0 0 . 0 5 10 0 . 0 5 10 0 . 0 30 0 . 0 60 0 . 0 5d a e r p s r e t n e c % 5 2 . 0 - / + 0110 0 0 0 . 0 0 16 6 . 6 6 15 2 . 1 30 5 . 2 60 0 . 0 5d a e r p s n w o d % 5 . 0 - o t 0 0110 1 3 3 . 3 3 16 6 . 6 6 13 3 . 3 36 6 . 6 60 3 . 5 5d a e r p s n w o d % 5 . 0 - o t 0 01110 0 0 . 0 5 10 0 . 0 0 10 0 . 0 30 0 . 0 60 0 . 0 5d a e r p s r e t n e c % 5 2 . 0 - / + 0111 1 0 0 . 0 6 10 0 . 0 2 10 0 . 0 30 0 . 0 60 0 . 8 4d a e r p s r e t n e c % 5 2 . 0 - / + 10 0 0 0 0 0 . 0 90 0 . 0 90 0 . 0 30 0 . 0 60 0 . 5 4d a e r p s r e t n e c % 5 2 . 0 - / + 10 0 0 1 0 9 . 0 0 10 9 . 0 0 13 6 . 3 37 2 . 7 65 4 . 0 5d a e r p s r e t n e c % 5 2 . 0 - / + 10 0 1 0 0 0 . 3 0 10 0 . 3 0 13 3 . 4 37 6 . 8 60 5 . 1 5d a e r p s r e t n e c % 5 2 . 0 - / + 10 0 1 1 0 9 . 3 3 10 9 . 3 3 18 4 . 3 37 6 . 8 66 5 . 1 5d a e r p s r e t n e c % 5 2 . 0 - / + 10 1 0 0 3 3 . 7 3 10 0 . 3 0 13 3 . 4 35 9 . 6 65 4 . 1 5d a e r p s r e t n e c % 5 2 . 0 - / + 10 1 0 1 3 3 . 7 3 13 3 . 7 3 13 3 . 4 37 6 . 8 61 2 . 0 5d a e r p s r e t n e c % 5 2 . 0 - / + 10 1 1 0 0 9 . 0 0 10 9 . 3 3 18 4 . 3 35 9 . 6 61 2 . 0 5d a e r p s r e t n e c % 5 2 . 0 - / + 10 1 1 1 0 9 . 3 3 10 9 . 0 0 18 4 . 3 35 9 . 6 61 2 . 0 5d a e r p s r e t n e c % 5 2 . 0 - / + 110 0 0 0 0 . 7 0 10 0 . 7 0 16 6 . 5 33 3 . 1 70 5 . 3 5d a e r p s r e t n e c % 5 2 . 0 - / + 110 0 1 0 0 . 7 0 16 6 . 2 4 16 6 . 5 33 3 . 1 70 5 . 3 5d a e r p s r e t n e c % 5 2 . 0 - / + 110 1 0 6 6 . 2 4 16 6 . 2 4 16 6 . 5 33 3 . 1 70 5 . 3 5d a e r p s r e t n e c % 5 2 . 0 - / + 110 1 1 0 0 . 0 1 10 0 . 0 1 16 6 . 6 33 3 . 3 70 0 . 5 5d a e r p s r e t n e c % 5 2 . 0 - / + 1110 0 0 0 . 0 1 16 6 . 6 4 16 6 . 6 33 3 . 3 70 0 . 5 5d a e r p s r e t n e c % 5 2 . 0 - / + 1110 1 6 6 . 6 4 16 6 . 6 4 16 6 . 6 33 3 . 3 70 0 . 5 5d a e r p s r e t n e c % 5 2 . 0 - / + 111 1 0 0 7 . 6 6 10 0 . 5 2 15 2 . 1 38 6 . 6 67 5 . 5 5d a e r p s r e t n e c % 5 2 . 0 - / + 111 1 1 0 0 . 0 0 20 0 . 0 0 23 3 . 3 36 6 . 6 60 0 . 0 5d a e r p s r e t n e c % 5 2 . 0 - / + 3 t i b s t u p n i d e h c t a l , t c e l e s e r a w d r a h y b d e t c e l e s s i y c n e u q e r f - 0 4 : 7 2 , t i b y b d e t c e l e s s i y c n e u q e r f - 1 0 1 t i b l a m r o n - 0 d e l b a n e m u r t c e p s d a e r p s - 1 1 0 t i b g n i n n u r - 0 s t u p t u o l l a e t a t s i r t - 1 0
5 ics9248-199 0376e?12/23/02 byte 5: cpu, active/inactive register (1= enable, 0 = disable) byte 6: pci, active/inactive register (1= enable, 0 = disable) byte 7: control, active/inactive register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b3 21 ) f f o : 0 , n o : 1 ( m 8 4 _ m 4 2 6 t i b3 , 20 l o r t n o c _ x 2 x 1 _ f e r ) x 2 : 1 , x 1 : 0 ( 5 t i b7 41 l o r t n o c _ x 2 x 1 c i p a ) x 2 : 1 , x 1 : 0 ( 4 t i b9 11 ) e v i t c a n i / t c a ( 1 k l c p g a 3 t i b8 11 ) e v i t c a n i / t c a ( 0 k l c p g a 2 t i b-0 t c e l e s c i p a o i ) z h m 3 3 . 3 3 : 1 , z h m 7 6 . 6 1 : 0 ( 1 t i b3 21 t c e l e s m 8 4 _ m 4 2 ) z h m 8 4 : 0 , z h m 4 2 : 1 ( 0 t i b2 20 d e v r e s e r t i b# n i pd w pn o i t p i r c s e d 7 t i b9 11 d e v r e s e r 6 t i b8 11 d e v r e s e r 5 t i b6 11 ) e v i t c a n i / t c a ( 4 k l c i c p 4 t i b5 11 ) e v i t c a n i / t c a ( 3 k l c i c p 3 t i b3 11 ) e v i t c a n i / t c a ( 2 k l c i c p 2 t i b2 11 ) e v i t c a n i / t c a ( 1 k l c i c p 1 t i b0 11 ) e v i t c a n i / t c a ( 0 k l c i c p 0 t i b3 2x ) k c a b d a e r ( l e s p g a t i b# n i pd w pn o i t p i r c s e d 7 t i b2 10 l o r t n o c _ x 2 x 1 _ 1 k l c l c p ) x 1 : 0 , x 2 : 1 ( 6 t i b3 10 l o r t n o c _ x 2 x 1 _ 2 k l c l c p ) x 1 : 0 , x 2 : 1 ( 5 t i b0 1x ) k c a b d a e r ( 3 s f 4 t i b9x ) k c a b d a e r ( 2 s f 3 t i b3x ) k c a b d a e r ( 1 s f 2 t i b2x ) k c a b d a e r ( 0 s f 1 t i b5 1x l o r t n o c _ x 2 x 1 _ 3 k l c l c p ) x 1 : 0 , x 2 : 1 ( 0 t i b6 1x l o r t n o c _ x 2 x 1 _ 4 k l c l c p ) x 1 : 0 , x 2 : 1 (
6 ics9248-199 0376e?12/23/02 byte 8: byte count read back register t i be m a nd w pn o i t p i r c s e d 7 t i b7 e t y b0 e r u g i f n o c l l i w r e t s i g e r s i h t o t g n i t i r w : e t o n e b l l i w s e t y b y n a m w o h d n a t n u o c e t y b f 0 s i t l u a f e d , k c a b d a e r h . s e t y b 5 1 = 6 t i b6 e t y b0 5 t i b5 e t y b0 4 t i b4 e t y b0 3 t i b3 e t y b1 2 t i b2 e t y b1 1 t i b1 e t y b1 0 t i b0 e t y b1 byte 10: programming enable bit 8 watchdog control register* byte 9: watchdog timer count register* t i be m a nd w pn o i t p i r c s e d 7 t i b m a r g o r p e l b a n e 0 t i b e l b a n e g n i m m a r g o r p y b d e t c e l e s e r a s e i c n e u q e r f . g n i m m a r g o r p o n = 0 0 e t y b r o s e h c t a l w h i l l a e l b a n e = 1 2 . g n i m a r g o r p c 6 t i be l b a n e d w0 t i b e l b a n e g o d h c t a w 5 t i bm r a l a d w0 s u t a t s m r a l a = 1 l a m r o n = 0 s u t a t s m r a l a g o d h c t a w 4 t i b4 f s0 s t i b e s e h t o t g n i t i r w . s t i b y c n e u q e r f e f a s g o d h c t a w o t g n i d n o p s r r o c y c n e u q e r f e f a s e h t e r u g i f n o c l l i w e l b a t 4 : 7 , 2 t i b 0 e t y b 3 t i b3 f s1 2 t i b2 f s0 1 t i b1 f s0 0 t i b0 f s0 t i be m a nd w pn o i t p i r c s e d 7 t i b7 d w0 s t i b 8 e s e h t f o n o i t a t n e s e r p e r l a m i c e d e h t g o d h c t a w e h t s m 0 9 2 x o t d n o p s e r r o c e d o m m r a l a o t s e o g t i e r o f e b t i a w l l i w r e m i t . g n i t t e s e f a s e h t o t y c n e u q e r f e h t t e s e r d n a 6 . 4 = s m 0 9 2 6 1 s i p u r e w o p t a t l u a f e d . s d n o c e s 6 t i b6 d w0 5 t i b5 d w0 4 t i b4 d w1 3 t i b3 d w0 2 t i b2 d w0 1 t i b1 d w0 0 t i b0 d w0 byte 11: vco frequency m divider (reference divider) control register* t i be m a nd w pn o i t p i r c s e d 7 t i b8 v i d nx 8 t i b r e d i v i d n 6 t i b6 v i d mx ) 0 : 6 ( v i d m f o n o i t a t n e s e r p s e r l a m i c e d e h t . e u l a v r e d i v i d e c n e r e f e r e h t o t d s o p s e r r o c d e h c t a l e h t o t l a u q e s i p u r e w o p t a t l u a f e d . n o i t c e l e s s t u p n i 5 t i b5 v i d mx 4 t i b4 v i d mx 3 t i b3 v i d mx 2 t i b2 v i d mx 1 t i b1 v i d mx 0 t i b0 v i d mx * these bytes are not available in ics9248a/b/cf-199. programmable features on these bytes are only for ics9248d/ef-199.
7 ics9248-199 0376e?12/23/02 byte 12: vco frequency n divider (vco divider) control register* t i be m a nd w pn o i t p i r c s e d 7 t i b7 v i d nx ) 0 : 8 ( v i d n f o n o i t a t n e s e r p e r l a m i c e d e h t . e u l a v r e d i v i d o c v e h t o t d n o p s e r r o c d e h c t a l e h t o t l a u q e s i p u r e w o p t a t l u a f e d n i d e t a c o l s i 8 v i d n e c i t o n . n o t c e l e s s t u p n i . 1 1 e t y b 6 t i b6 v i d nx 5 t i b5 v i d nx 4 t i b4 v i d nx 3 t i b3 v i d nx 2 t i b2 v i d nx 1 t i b1 v i d nx 0 t i b0 v i d nx byte 13: spread spectrum control register* t i be m a nd w pn o i t p i r c s e d 7 t i b7 s sx l l i w t i b ) 0 : 2 1 ( m u r t c e p s d a e r p s e h t d a e r p s . e g a t n e c e r p d a e r p s e h t m a r g o r p n o d e s a b d e t a l u c l a c e b o t s d e e n t n e c e r p , e l i f o r p g n i d a e r p s , y c n e u q e r f o c v e h t t i . y c n e u q e r f d a e r p s d n a t n u o m a g n i d a e r p s r o f e r a w t f o s s c i e s u o t d e d n e m m o c e r s i s i n o r e w o p t l u a f e d . g n i m m a r g o r p d a e r p s . r e d i v i d s f d e h c t a l 6 t i b6 s sx 5 t i b5 s sx 4 t i b4 s sx 3 t i b3 s sx 2 t i b2 s sx 1 t i b1 s sx 0 t i b0 s sx byte 14: spread spectrum control register* byte 15: output divider control register* t i be m a nd w pn o i t p i r c s e d 7 t i bd e v r e s e rxd e v r e s e r 6 t i bd e v r e s e rxd e v r e s e r 5 t i bd e v r e s e rxd e v r e s e r 4 t i b2 1 s sx 2 1 t i b m u r t c e p s d a e r p s 3 t i b1 1 s sx 1 1 t i b m u r t c e p s d a e r p s 2 t i b0 1 s sx 0 1 t i b m u r t c e p s d a e r p s 1 t i b9 s sx 9 t i b m u r t c e p s d a e r p s 0 t i b8 s sx 8 t i b m u r t c e p s d a e r p s t i be m a nd w pn o i t p i r c s e d 7 t i b3 v i d d sx e b n a c o i t a r r e d i v i d k c o l c m a r d s . y l l a u d i v i d n i s t i b 4 e s e h t a i v d e r u g i f n o c o t r e f e r e l b a t n o i t c e l e s r e d i v i d r o f d e h c t a l s i p u r e w o p t a t l u a f e d . 1 e l b a t . r e d i v i d s f 6 t i b2 v i d d sx 5 t i b1 v i d d sx 4 t i b0 v i d d sx 3 t i b3 v i d u p cx e b n a c o i t a r r e d i v i d k c o l c u p c . y l l a u d i v i d n i s t i b 4 e s e h t a i v d e r u g i f n o c o t r e f e r e l b a t n o i t c e l e s r e d i v i d r o f d e h c t a l s i p u r e w o p t a t l u a f e d . 1 e l b a t . r e d i v i d s f 2 t i b2 v i d u p cx 1 t i b1 v i d u p cx 0 t i b0 v i d u p cx * these bytes are not available in ics9248a/b/cf-199. programmable features on these bytes are only for ics9248d/ef-199.
8 ics9248-199 0376e?12/23/02 byte 16: output divider control register* byte 17: output divider control register* t i be m a nd w pn o i t p i r c s e d 7 t i b3 v i d i c px e b n a c o i t a r r e d i v i d k c o l c i c p s t i b 4 e s e h t a i v d e r u g i f n o c n o i t c e l e s r e d i v i d r o f . y l l a u d i v i d n i t a t l u a f e d . 2 e l b a t o t r e f e r e l b a t . r e d i v i d s f d e h c t a l s i p u r e w o p 6 t i b2 v i d i c px 5 t i b1 v i d i c px 4 t i b0 v i d i c px 3 t i b3 v i d z h m 0 5 p g ax e b n a c o i t a r r e d i v i d k c o l c p g a s t i b 4 e s e h t a i v d e r u g i f n o c n o i t c e l e s r e d i v i d r o f . y l l a u d i v i d n i t a t l u a f e d . 1 e l b a t o t r e f e r e l b a t . r e d i v i d s f d e h c t a l s i p u r e w o p 2 t i b2 v i d z h m 0 5 p g ax 1 t i b1 v i d z h m 0 5 p g ax 0 t i b0 v i d z h m 0 5 p g ax t i be m a nd w pn o i t p i r c s e d 7 t i bd e v r e s e rxd e v r e s e r 6 t i bd e v r e s e rxd e v r e s e r 5 t i bv n i _ d sx t i b n o i s r e v n i e s a h p m a r d s 4 t i bv n i _ u p cx t i b n o i s r e v n i e s a h p k l c u p c 3 t i b3 v i d z h m 6 6 p g ax e b n a c o i t a r r e d i v i d k c o l c p g a s t i b 4 e s e h t a i v d e r u g i f n o c n o i t c e l e s r e d i v i d r o f . y l l a u d i v i d n i t a t l u a f e d . 1 e l b a t o t r e f e r e l b a t . r e d i v i d s f d e h c t a l s i p u r e w o p 2 t i b2 v i d z h m 6 6 p g ax 1 t i b1 v i d z h m 6 6 p g ax 0 t i b0 v i d z h m 6 6 p g ax table 1 table 2 ) 2 : 3 ( v i d 0 01 00 11 1 ) 0 : 1 ( v i d 0 02 /4 /8 /6 1 / 1 03 /6 /2 1 /4 2 / 0 15 /0 1 /0 2 /0 4 / 1 17 /4 1 /8 2 /6 5 / ) 2 : 3 ( v i d 0 01 00 11 1 ) 0 : 1 ( v i d 0 04 /8 /6 1 /2 3 / 1 03 /6 /2 1 /4 2 / 0 15 /0 1 /0 2 /0 4 / 1 17 /4 1 /8 2 /6 5 / * these bytes are not available in ics9248a/b/cf-199. programmable features on these bytes are only for ics9248d/ef-199.
9 ics9248-199 0376e?12/23/02 byte 19: group skew control register* byte 20: group skew control register* byte 18: group skew control register* t i be m a nd w pn o i t p i r c s e d 7 t i b3 w e k s _ c i p a0 o t k l c u p c e h t e g n a h c n a c s t i b 4 e s e h t t a t l u a f e d . s n 9 . 2 - s n 4 . 1 m o r f w e k s c i p a t n e m e r c n i y r a n i b h c a e . s n 5 . 2 - s i p u r e w o p l l i w ) 0 : 3 ( w e k s _ c i p a f o t n e m e r c e d r o u p c e h t f o y a l e d e h t e s a e r c e d r o e s a e r c n i . s p 0 0 1 y b s k c o l c 6 t i b2 w e k s _ c i p a0 5 t i b1 w e k s _ c i p a1 4 t i b0 w e k s _ c i p a0 3 t i b0 f e r1 ) e v i t c a n i / t c a ( 1 f e r 2 t i b1 f e r1 ) e v i t c a n i / t c a ( 0 f e r 1 t i bc i p a o i1 ) e v i t c a n i / t c a ( c i p a o i 0 t i bz h m 8 41 ) e v i t c a n i / t c a ( z h m 8 4 t i be m a nd w pn o i t p i r c s e d 7 t i b1 w e k s _ u p c1 h t i w s k c o l c u p c e h t y a l e d s t i b 2 e s e h t . s k c o l c r e h t o l l a o t t c e p s e r s p 0 5 2 = 1 0 s p 0 = 0 0s p 0 5 7 = 1 1 s p 0 0 5 = 0 1 6 t i b0 w e k s _ u p c0 5 t i b1 w e k s _ d s0 h t i w t u o _ m a r d s e h t y a l e d s t i b 2 e s e h t k l c u p c o t t c e p s e r s p 0 5 7 = 1 1 s p 0 0 5 = 0 1 s p 0 5 2 = 1 0 s p 0 = 0 0 4 t i b0 w e k s _ d s0 3 t i b3 w e k s _ i c p0 o t k l c u p c e h t e g n a h c n a c s t i b 4 e s e h t y r a n i b h c a e . s n 9 . 2 - s n 4 . 1 m o r f w e k s k l c i c p ) 0 : 3 ( w e k s _ i c p f o t n e m e r c e d r o t n e m e r c n i i c p e h t f o y a l e d e h t e s a e r c e d r o e s a e r c n i l l i w . s p 0 0 1 y b s k c o l c ) 1 : 0 , f ( 2 t i b2 w e k s _ i c p0 1 t i b1 w e k s _ i c p1 0 t i b0 w e k s _ i c p0 t i be m a nd w pn o i t p i r c s e d 7 t i b3 w e k s _ p g a0 o t k l c u p c e h t e g n a h c n a c s t i b 4 e s e h t t a t l u a f e d . s n 9 . 2 - s n 4 . 1 m o r f w e k s p g a r o t n e m e r c n i y r a n i b h c a e . s n 5 . 2 - s i p u r e w o p e s a e r c n i l l i w ) 0 : 3 ( w e k s _ p g a f o t n e m e r c e d y b s k c o l c p g a e h t f o y a l e d e h t e s a e r c e d r o . s p 0 0 1 6 t i b2 w e k s _ p g a0 5 t i b1 w e k s _ p g a1 4 t i b0 w e k s _ p g a0 3 t i b3 w e k s _ i c p0 i c p o t k l c u p c e h t e g n a h c n a c s t i b 4 e s e h t y r a n i b h c a e . s n 9 . 2 - s n 4 . 1 m o r f w e k s ) 0 : 3 ( w e k s _ i c p f o t n e m e r c e d r o t n e m e r c n i i c p e h t f o y a l e d e h t e s a e r c e d r o e s a e r c n i l l i w . s p 0 0 1 y b s k c o l c ) 4 : 2 ( 2 t i b2 w e k s _ i c p0 1 t i b1 w e k s _ i c p1 0 t i b0 w e k s _ i c p0 * these bytes are not available in ics9248a/b/cf-199. programmable features on these bytes are only for ics9248d/ef-199.
10 ics9248-199 0376e?12/23/02 byte 23: slew rate control register* byte 22: slew rate control register* byte 21: slew rate control register* t i be m a nd w pn o i t p i r c s e d 7 t i b1 w e l s _ 8 4 / 4 20 . s t i b l o r t n o c e t a r w e l s k c o l c z h m 8 4 / 4 2 k a e w = 0 1 ; l a m r o n = 1 1 , 0 0 ; g n o r t s = 1 0 6 t i b0 w e l s _ 8 4 / 4 21 5 t i b1 w e l s _ p g a0 . s t i b l o r t n o c e t a r w e l s k c o l c p g a k a e w = 1 0 ; l a m r o n = 1 1 , 0 0 ; g n o r t s = 0 1 4 t i b0 w e l s _ p g a1 3 t i b1 w e l s _ c i p a0 . s t i b l o r t n o c e t a r w e l s k c o l c c i p a o i k a e w = 0 1 ; l a m r o n = 1 1 , 0 0 ; g n o r t s = 0 0 2 t i b0 w e l s _ c i p a1 1 t i b1 w e l s _ f e r0 . s t i b l o r t n o c e t a r w e l s k c o l c f e r k a e w = 0 0 ; l a m r o n = 1 1 , 0 0 ; g n o r t s = 0 1 0 t i b0 w e l s _ f e r1 t i be m a nd w pn o i t p i r c s e d 7 t i bd e v r e s e r0d e v r e s e r 6 t i bd e v r e s e r0d e v r e s e r 5 t i bx 2 x 1 f _ k l c i c p0x 2 : 1 , x 1 : 0 4 t i b0 k l c i c p0x 2 : 1 , x 1 : 0 3 t i bd e v r e s e r0d e v r e s e r 2 t i bd e v r e s e r0d e v r e s e r 1 t i bd e v r e s e r0d e v r e s e r 0 t i bd e v r e s e r0d e v r e s e r t i be m a nd w pn o i t p i r c s e d 7 t i b 1 w e l s z h m 8 4 0 . s t i b l o r t n o c e t a r w e l s k c o l c z h m 8 4 k a e w = 0 1 ; l a m r o n = 1 1 , 0 0 ; g n o r t s = 1 0 6 t i b1 5 t i b c / t k l c u p c 1 w e l s 0 . t i b l o r t n o c e t a r w e l s k c o l c 0 c / t k l c u p c k a e w = 0 1 ; l a m r o n = 1 1 , 0 0 ; g n o r t s = 1 0 4 t i b1 3 t i b k l c u p c1 w e l s 0 . s t i b l o r t n o c e t a r w e l s k c o l c k l c u p c k a e w = 0 1 ; l a m r o n = 1 1 , 0 0 ; g n o r t s = 1 0 2 t i b1 1 t i b d s1 w e l s 0 . s t i b l o r t n o c e t a r w e l s k c o l c m a r d s k a e w = 0 1 ; l a m r o n = 1 1 , 0 0 ; g n o r t s = 1 0 0 t i b1 * these bytes are not available in ics9248a/b/cf-199. programmable features on these bytes are only for ics9248d/ef-199. bit 24: control, active/inactive register* (1 = enable, 0 = disable) bit pin# pwd description bit 7 - 0 reserved bit 6 - 0 reserved bit 5 - 0 reserved bit 4 - 0 reserved bit 3 9 0 pciclk_f (act/inactive) bit 2 44 0 cpuclkt0 (act/inactive) bit 1 43 0 cpuclk_c0 (act/inactive) bit 0 40 1 cpuclk (act/inactive)
11 ics9248-199 0376e?12/23/02 absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . 0c to +70c case temperature . . . . . . . . . . . . . . . . . . . . . . 115c storage temperature . . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/s upply/common output parameters t a = 0 - 70c; supply volta g e v dd = 3.3 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2v dd + 0.3 v input low voltage v il v ss - 0.3 0.8 v i dd 134 180 ma i ddl 27 39 ma power down pd 280 600 ua input frequency f i v dd = 3.3 v 12 14.318 16 mhz c in logic inputs 5 pf c inx x1 & x2 pins 27 45 pf transistion time 1 t trans to 1st crossing of target frequency 3 ms settling time 1 t s from 1st crossing to 1% of target frequency ms clk stabilization 1 t stab from v dd = 3.3 v to 1% of target frequency 11 15 ms skew 1 t cpu - pci v t = 1.5 v; v tl = 50% v dd 11.8 4 ns skew 1 t cpu - agp v t = 1.5 v; v tl = 50% v dd 11.6 4 ns 1 guaranteed by design, not 100% tested in production. input capacitance 1 operating supply current c l =30 pf pci, sdram, 20 pf other outputs
12 ics9248-199 0376e?12/23/02 electrical characteristics - cpuclk (open drain) t a = 0 - 70c; v dd =3.3v +/- 5%; c l = 20 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance z o 1 v o =v x 50 ? output high voltage v oh2b termination to vpull-up(external) 1 1.2 v output low voltage v ol2b termination to vpull-up(external) 0.4 v output low current i ol2b v ol = 0.3 v 18 ma v oh = 1.1v, v ol = 2.0v 1.7 2 v oh = 80% v dd , v ol = 20% v dd 1.1 1.2 differential voltage-ac 1 v dif note 2 0.4 vpull-up(ext) + 0.6 v differential voltage-dc 1 v dif note 2 0.2 vpull-up(ext) + 0.6 v diff crossover voltage 1 v x note 3 1.2 1.45 1.6 v cput0,c0 between crossing poi n 45 53 55 cput0,c0 v t = 50% v dd 44 47 55 skew cpuclk to cput0 1 t sk2b 1 v t = 50% 40 175 ps jitter, cycle-to-cycle 1 tjcyc-cyc 2b 1 v t = v x 105 250 ps jitter, absolute 1 tjabs 2b 1 v t = 50% -250 250 ps notes: 1 - guaranteed by design, not 100% tested in production. 2 - v dif specifies the minimum input differential voltages (v tr -v cp ) required for switching, where v tr is the "true" input level and v cp is the "complement" input level. 3 - vpull-up(external) = 2.7v, min=vpull-up(external)/2-150mv; max=vpull-up(external)/2 +150mv % d t2b 1 duty cycle 1 fall time 1 t f2b 1 ns electrical characteristics - 24mhz, 48mhz, agp, ref t a = 0 - 70c; v dd = 3.3v +/-5%; c l = 20 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance 1 r dsp5b v o =v dd *(0.5) 20 60 ? output impedance 1 r dsn5b v o =v dd *(0.5) 20 60 ? output high voltage v oh5 i oh = -14 ma 2.4 v output low voltage v ol5 i ol = 6 ma 0.4 v output high current i oh5 v oh = 2.0 v -20 ma output low current i ol5 v ol = 0.8 v 10 ma rise time 1 t r5 1 v ol = 0.4 v, v oh = 2.4 v 1.3 2 ns fall time 1 t f5 1 v oh = 2.4 v, v ol = 0.4 v 1.3 2 ns v t = 1.5 v 24_48 mhz, agp 45 52 55 v t = 1.5 v ref 45 55 56 skew agp to agp 1 t sk5 1 v t = 1.5 v agp 100 175 ps v t = 1.5 v 24_48 mhz 110 500 v t = 1.5 v agp 220 v t = 1.5 v ref 375 500 1 guaranteed by design, not 100% tested in production. % duty cycle 1 d t5 1 ps jitter, cycle-to-cycle 1 t jcyc-cyc5 1
13 ics9248-199 0376e?12/23/02 electrical characteristics - pciclk t a = 0 - 70c; v dd = 3.3v +/-5%; c l = 30 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance 1 r dsp1b v o =v dd *(0.5) 12 55 ? output impedance 1 r dsn1b v o =v dd *(0.5) 12 55 ? output high voltage v oh1 i oh = -18 ma 2.6 v output low voltage v ol1 i ol = 9.4 ma 0.4 v output high current i oh1 v oh = 2.0 v -22 ma output low current i ol1 v ol = 0.8 v 25 ma rise time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 1.7 2.0 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 1.8 2.0 ns dut y c y cle 1 d t1 v t = 1.5 v 455155% skew window 1 t sk1 v t = 1.5 v 170 500 ps jitter, cycle-to-cycle 1 t cyc-cyc1 v t = 1.5 v 265 500 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - sdram t a = 0 - 70c; v dd =3.3v +/-5%; c l = 30 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance 1 r dsp3 v o =v dd *(0.5) 10 20 ? output impedance 1 r dsn3 v o =v dd *(0.5) 10 20 ? output high voltage v oh3 i oh = -28 ma 2.4 v output low voltage v ol3 i ol = 19 ma 0.4 v output high current i oh3 v oh = 2.0 v -42 ma output low current i ol3 v ol = 0.8 v 33 ma rise time 1 t r3 v ol = 0.4 v, v oh = 2.4 v 0.8 1.5 ns fall time 1 t f3 v oh = 2.4 v, v ol = 0.4 v 0.6 1.5 ns dut y c y cle 1 d t3 v t = 1.5 v 455055% v t = 1.5 v 100, 133 mhz 150 250 166 mhz 280 350 1 guaranteed by design, not 100% tested in production. jitter, cycle-to-cycle 1 t cyc-cyc3 ps
14 ics9248-199 0376e?12/23/02 electrical characteristics - ioapic t a = 0 - 70c; v dd = 3.3v +/-5%; c l = 20 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance 1 r dsp4b v o =v dd *(0.5) 20 60 ? output impedance 1 r dsn4b v o =v dd *(0.5) 20 60 ? output high voltage v oh4 i oh = -14 ma 2.4 v output low voltage v ol4 i ol = 6 ma 0.4 v output high current i oh4 v oh = 2.0 v -20 ma output low current i ol4 v ol = 0.8 v 10 ma rise time 1 t r4 v ol = 0.4 v, v oh = 2.4 v 0.7 2 ns fall time 1 t f4 v oh = 2.4 v, v ol = 0.4 v 0.8 2 ns duty cycle 1 d t4 v t = 1.5 v 24_48 mhz, agp 45 50 55 % jitter, cycle-to-cycle 1 t jcyc-cyc4 v t = 1.5 v 24_48 mhz 235 500 ps 1 guaranteed by design, not 100% tested in production.
15 ics9248-199 0376e?12/23/02 general i 2 c serial interface information how to write: ? controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) sends the data byte count = x ics clock will acknowledge controller (host) starts sending byte n through byte n + x -1 (see note 2) ics clock will acknowledge each byte one at a time controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) will send a separate start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the data byte count = x ics clock sends byte n + x -1 ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . controller (host) will need to acknowledge each byte controllor (host) will send a not acknowledge bit controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p stop bit x byte index block write operation slave address d2 (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit slave address d3 (h) index block read operation slave address d2 (h) beginning byte = n ack ack data byte count = x ack ics (slave/receiver) controller (host) x byte ack ack
16 ics9248-199 0376e?12/23/02 fig. 1 shared pin operation - input/output pins the i/o pins designated by (input/output) on the ics9248- 199 serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm (10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. via to vdd clock trace to load series term. res. programming header via to gnd device pad 2k 8.2k figure 1 shows a means of implementing this function when a switch or 2 pin header is used. with no jumper is installed the pin will be pulled high. with the jumper in place the pin will be pulled low. if programmability is not necessary, than only a single resistor is necessary. the programming resistors should be located close to the series termination resistor to minimize the current loop area. it is more important to locate the series termination resistor close to the driver than the programming resistor.
17 ics9248-199 0376e?12/23/02 cpu_stop# timing diagram cpu_stop# is an asychronous input to the clock synthesizer. it is used to turn off the cpu clocks for low power operation. cpu_stop# is synchronized by the ics9248-199 . the minimum that the cpu clock is enabled (cpu_stop# high pulse) is 100 cpu clocks. all other clocks will continue to run while the cpu clocks are disabled. the cpu clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. cpu clock on latency is less than 4 cpu clocks and cpu clock off latency is less than 4 cpu clocks. notes: 1. all timing is referenced to the internal cpu clock. 2. cpu_stop# is an asynchronous input and metastable conditions may exist. this signal is synchronized to the cpu clocks inside the ics9248-199. 3. all other clocks continue to run undisturbed. pciclk cpuclkt cpuclkc pd# (high) cpu_stop# internal cpuclk
18 ics9248-199 0376e?12/23/02 pci_stop# timing diagram pci_stop# is an asynchronous input to the ics9248-199 . it is used to turn off the pciclk clocks for low power operation. pci_stop# is synchronized by the ics9248-199 internally. the minimum that the pciclk clocks are enabled (pci_stop# high pulse) is at least 10 pciclk clocks. pciclk clocks are stopped in a low state and started with a full high pulse width guaranteed. pciclk clock on latency cycles are only one rising pciclk clock off latency is one pciclk clock. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the ics9248-199 device.) 2. pci_stop# is an asynchronous input, and metastable conditions may exist. this signal is required to be synchronized inside the ics9248-199. 3. all other clocks continue to run undisturbed. 4. cpu_stop# is shown in a high (true) state.
19 ics9248-199 0376e?12/23/02 sdram_stop# timing diagram sdram_stop# is an asychronous input to the clock synthesizer. it is used to stop sdram clocks for low power operation. sdram_stop# is synchronized to complete it's current cycle, by the ics9248-199 . all other clocks will continue to run while the sdram clocks are disabled. the sdram clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. notes: 1. all timing is referenced to the internal cpu clock. 2. sdram is an asynchronous input and metastable conditions may exist. this signal is synchronized to the sdram clocks inside the ics9248-199. 3. all other clocks continue to run undisturbed.
20 ics9248-199 0376e?12/23/02 pd# timing diagram the power down selection is used to put the part into a very low power state without turning off the power to the part. pd# is an asynchronous active low input. this signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. internal clocks are not running after the device is put in power down. when pd# is active low all clocks need to be driven to a low value and held prior to turning off the vcos and crystal. the power up latency needs to be less than 3 ms. the power down latency should be as short as possible but conforming to the sequence requirements shown below. pci_stop# and cpu_stop# are considered to be don't cares during the power down operations. the ref and 48mhz clocks are expected to be stopped in the low state as soon as possible. due to the state of the internal logic, stopping and holding the ref clock outputs in the low state may require more than one clock cycle to complete. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the ics9248-199 device). 2. as shown, the outputs stop low on the next falling edge after pd# goes low. 3. pd# is an asynchronous input and metastable conditions may exist. this signal is synchronized inside this part. 4. the shaded sections on the vco and the crystal signals indicate an active clock. 5. diagrams shown with respect to 133mhz. similar operation when cpu is 100mhz. cpuclkt cpuclkc pciclk vco crystal pd#
21 ics9248-199 0376e?12/23/02 ordering information ics9248 y f-199-t designation for tape and reel packaging pattern number (2 or 3 digit number for parts with rom code patterns) package type f = ssop revision designator (will not correlate with datasheet revision) device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx y f - ppp - t index area index area 12 1 2 n d h x 45 h x 45 e1 e seating plane seating plane a1 a e -c- - c - b .10 (.004) c .10 (.004) c c l 300 mil ssop package min max min max a 2.41 2.80 .095 .110 a1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 d e 10.03 10.68 .395 .420 e1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 l 0.50 1.02 .020 .040 n 0 8 0 8 min max min max 48 15.75 16.00 .620 .630 10-0034 reference doc.: jedec publication 95, mo-118 variations see variations see variations n d mm. d (inch) see variations see variations 0.635 basic 0.025 basic symbol in millimeters in inches common dimensions common dimensions

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